8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating

Abstract

A graphics execution core in 22nm combines SRAM array-assist circuits to lower intrinsic VMIN, retention flops to reduce leakage power during stall periods, and a fully integrated hybrid digital LDO/SCVR regulator to provide a cost-effective means to realize autonomous DVFS under a shared-rail scenario [1–2]. In a conventional design, a conservative voltage guard band (VGB) is added to the nominal supply of each die to guarantee its correct operation at target frequency in the presence of worst-case delay degradation induced by inverse-temperature dependency (ITD) [3], device aging, and voltage droop. This VGB is determined from post-silicon characterization as the voltage shift needed by the worst-case die, assuming extreme aging usage conditions, while running a power virus load. In this paper, we present a graphics execution core that uses an in-situ tunable replica circuit (TRC) [4–5] to monitor critical timing margin and trigger adaptive voltage scaling (AVS) as needed to dynamically adjust VCC during run time (Fig. 8.4.1). The TRC monitors slow variations in temperature and aging and provides a time-to-digital converter (TDC) code, representing the timing margin measurement, to the AVS controller. Based on the TDC code, the AVS controller communicates a new voltage ID (VID) to the external voltage regulator module (VRM) to maintain minimum VCC necessary to meet a given performance level.