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Abstract
This paper presents a practical solution to improving system level Verification and Validation (V&V) tests, those tests which exercise end‐to‐end functionality of a physical system, for complex hardware/software systems. The proposed method to improve system level testing is to increase the total number of system configurations that are tested in a way such that the state space coverage is explored in a systematic and evenly‐distributed fashion. We describe a method for adapting the combinatorial software test strategy known as t‐wise testing to complex hardware/software systems V&V testing. Practical requirements and potential test selection architecture are provided to demonstrate the utility of the proposed t‐wise testing method. Some methods for test selection and prioritization are outlined for instances when complete t‐wise testing is impractical.
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