Abstract

In this paper, the design of a 77.3 GHz Standing-Wave oscillator (SWO) is presented. The proposed SWO relies on the distribution of varactors along an asymmetrical slow-wave coplanar stripline, which enables the improvement of the quality factor of the tunable resonator, resulting in superior performance in terms of phase noise and DC-to-RF efficiency. The design methodology, based on the use of analytical models and abaci, is presented in detail and applied to a design in a 55-nm CMOS technology. With a core consumption of 15.1 mW, the proposed SWO operates from 76.09 GHz to 78.60 GHz and presents a phase noise of -115.1 dBc/Hz at 10 MHz offset, leading to a Figure of Merit (FOM) of -181 dBc/Hz. The DC-to-RF efficiency obtained is 3.1%.

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