Abstract
65-nm CMOS element of matching for content-addressable memory resilient to impact of single nuclear particles is proposed. Element includes upset-hardened STG DICE memory cell and XOR logical gate based on two tristate inverters. Transistors of the element are separated into two identical joint groups spaced on the chip by distance of more than 4 μm, which practically excludes the possibility of cell upset under impact of single nuclear particles. Designed element of matching is implemented in resilient to single event effects translation lookaside buffer of microprocessor.
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