6 - Enhancing Performance with Pipelining

Abstract

Pipelining is a technique that exploits parallelism among the instructions in a sequential instruction stream. It has the substantial advantage that unlike some speedup techniques, it can be invisible to the programmer. This chapter reviews the concept of pipelining using the millions of instructions per second (MIPS) instruction subset and a simplified version of its pipeline. It discusses the problems that pipelining introduces and the performance attainable under typical situations. The chapter also examines some advanced techniques that can be used to overcome the difficulties encountered in pipelined machines and discusses the way by which the pipelining works. Pipelining improves the average execution time per instruction. Depending on whether one starts with a single-cycle or multiple-cycle datapath, this reduction can be thought of as decreasing the clock cycle time or as decreasing the number of clock cycles per instruction (CPI). The chapter discusses the simple single-cycle datapath and pipelining is presented as reducing the clock cycle time of the simple datapath.