55-nm SiGe BiCMOS Distributed Amplifier Topologies for Time-Interleaved 120-Gb/s Fiber-Optic Receivers and Transmitters

Abstract

Two distributed circuits based on MOS-HBT cascodes are reported in a 55-nm SiGe BiCMOS technology and are aimed at a single-chip time-interleaved transceiver for future 1-Tb/s optical links. The first, a DC-135-GHz single-ended distributed amplifier (DA) was optimized for low noise, linear receivers, and has a measured noise figure (NF) $ 7 dB up to 88.5 GHz, 800 mVpp of linear input range, and 8.5 dB gain. Operation was confirmed with PRBS-31 eye diagram measurements up to 120 Gb/s. Additionally, a novel time-interleaved distributed power DAC test circuit was implemented as a proof-of-concept to investigate the maximum achievable output bandwidth at a differential output voltage swing of 6 Vpp, as needed to directly drive an optical modulator. Simulations of the doubly segmented 6-bit DAC show 4-PAM output eye diagrams at up to 120 GBaud. The measured clock-input-to-data-output small-signal bandwidth is 65 GHz. When the DAC is measured as a switching large-swing driver, the differential output voltage swing remains larger than $5.4~\text {V}_{\mathrm {pp}}$ beyond 50 Gb/s. Time interleaving of 4 thermometer MSBs is demonstrated experimentally to form a 1.8- $\text{V}_{\text {pp}}$ differential, 10-GBaud 3-PAM output signal. The experimental sampling rate is limited to 10 GS/s by the capacitance and bandwidth of the low-frequency probes and pads used for the data lanes.