5.5 A quadrature relaxation oscillator with a process-induced frequency-error compensation loop

Abstract

With the emergence of wearable and implantable technologies, there has been growing demand on development of key enabling circuits for ultra-low-power sensor interface SoCs. As a reference-frequency generation block for clock management of the overall system, the relaxation oscillator has been widely adopted since it can provide a controllable and well-defined untrimmed frequency with low-cost circuits. In the past decade, the major goal in the design of the relaxation oscillators has been the improvement of phase-noise figure-of-merit (FOM) closer to the fundamental limit of 169dBc/Hz [1]. There have been feedback approaches to internally generate reference voltages for comparison, hence compensating the comparator circuit delay [2–4]. Since the delay compensation relies on the feedback operation, power consumption by analog circuits to meet the required bandwidth of the feedback loop eventually limits FOM. Recently, a swing-boosted differential scheme was proposed to reduce the effect of comparator noise by boosting the signal slope at the comparator input, demonstrating an FOM of over 160dBc/Hz [5]. However, the boosted voltage swing can increase stress on the input transistors of the comparator. In addition, a high-speed comparator is also needed to reduce the effect of the circuit delay on the output frequency. While most of previous works achieved good FOMs with MHz oscillators, implementation of low-frequency relaxation oscillators presents additional challenges since it requires excessive area for RC and power consumption by analog circuits with leakage not scaled down along with the output frequency.