50 nm SOI CMOS transistors with ultra shallow junction using laser annealing and pre-amorphization implantation

Cheolmin Park Cheolmin Park,Yun Wang Yun Wang,Seong-Dong Kim Seong-Dong Kim,S Talwar ,J.c.s Woo

doi:10.1109/vlsit.2001.934951

50 nm SOI CMOS transistors with ultra shallow junction using laser annealing and pre-amorphization implantation

Cheolmin Park Cheolmin Park, Yun Wang Yun Wang + Show 3 more

https://doi.org/10.1109/vlsit.2001.934951

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Publication Date: Jun 12, 2001

Citations: 11

Affiliation: University of California, Los Angeles

#Pre-amorphization Implantation #SOI Substrate + Show 8 more

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Abstract

CMOS transistors with 50 nm physical gate length are fabricated by laser annealing (LA) combined with pre-amorphization implantation (PAI) on an SOI substrate. Very low energy laser annealing is made possible by the SOI substrate, resulting in a large process window margin without undesirable parasitic phenomena. The transistors fabricated by the proposed method show higher drive current and better short channel effects than conventionally rapid thermal annealed (RTA) devices.

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