5.6‐GHz fractional‐N frequency synthesizer chip design with tunable Gm‐C loop filter

Abstract

ABSTRACTA 5.6‐GHz fractional‐N frequency synthesizer with a tunable Gm‐C filter is implemented in TSMC CMOS 0.18‐μm process. The proposed prototype is with a tunable loop filter bandwidth and hence, the process variations of passive elements of resistance and capacitance can be decreased and the chip area is greatly reduced. Moreover, MASH 1‐1‐1 sigma–delta (ΣΔ) modulator is adopted for performing the fractional division number and then, improves the phase noise as well. At 1.8‐V supply voltage, measured results achieve the locked phase noise of −114.1 dBc/Hz with lower Gm‐C bandwidth and −111.7 dBm/C with higher Gm‐C bandwidth at 1‐MHz offset from carrier of 5.68 GHz. The tuning range from 5.25 to 5.75 GHz, about 500 MHz, corresponding to 9.1% with a tunable voltage of 0–1.8 V, and including pads, the chip area of 0.715 × 0.78 (0.558) mm2. The output power is −8.69 dBm at 5.68 GHz and consumes 56 mW. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:2536–2541, 2013