Abstract
This paper details the development of a 0.18 /spl mu/m CMOS based amplifier core for the 802.11a standard. The amplifier core operates at 5.5 GHz and includes an adaptive biasing scheme to linearise the amplifier under high input power. Measurement results confirm that this linearisation scheme extends the 1 dB compression point by 4 dB over an unlinearised amplifier core. The supply voltage and bias current for the linearised amplifier are 1.8 V and 5.5 mA respectively, delivering 2 dBm into a 50 /spl Omega/ load when operated at the 1 dB compression point of -3.3 dBm. All the components of the linearisation scheme are implemented on-chip enabling maintenance of a single chip transceiver solution.
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