Abstract
In this paper, we proposed a block parallel architecture of interpolation for high-performance H.264/AVC Motion Compensation in 4K UHD() video real time processing. To improve throughput, we design block parallel interpolation. For supplying the reference data for interpolation, we design 2D cache buffer which consists of the memory arrays. We minimize redundant storage of the reference pixel by applying the Search Area Stripe Reuse scheme(SASR), and implement high-speed plane interpolator with 3-stage pipeline(Horizontal Vertical 1/2 interpolation, Diagonal 1/2 interpolation, 1/4 interpolation). The proposed architecture was simulated in 0.13um standard cell library. The maximum operation frequency is 150MHz. The gate count is 161Kgates. The proposed H.264/AVC Motion Compensation can support 4K UHD at 72 frames per second by running at 150MHz.
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