4H-SiC Trench-gate MOSFET with JTE termination

Abstract

4H-SiC Trench-gate MOSFET with JTE terminationIn this paper, a 4H-SiC trench-gate MOSFET is reported with detailed introduction on cell design, fabrication and characterization. The proposed trench-gate MOSFET features an asymmetric cell structure, in which the channels are distributed along a-face (11-20). High energy Al ion implantation is utilized to form deep P+ shielding region, which alleviates the electric field crowding in the oxide layer at the bottom of gate trench. In terms of the termination, a JTE structure is designed and realized with single-step ICP etching. The proposed 4H-SiC trench-gate MOSFET is fabricated on a 4-inch epitaxial wafer with a 3-layer P/N/N-design. After electrode patterning, the devices are tested and characterized on wafer with B1505A. Based on the measurement results, analysis and discussion are presented.