Abstract
A separate register file memory is included in at least two units of a pipelined processor which are located on separate integrated circuit chips. The register file memories of the units are interconnected so as to share certain input data register stages to enable updating to take place within a minimum of time. Each unit has a microprogrammed control unit which automatically provides update commands during the unit's cycles of operation. The signals from each microprogrammed control unit are applied to both register file memories enabling both memories to be updated during successive cycles of operation and thereby function collectively as one unit. This ensures that both units have access to the same most recently updated user visible information enabling both units to complete the execution of different instructions entering pipeline.
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