Abstract
A reconfigurable circuit operating in a test mode and a normal operating mode includes a memory array (10) which has a row decoder (12) for addressing the memory elements therein. The row decoder (12) has a fused switch (18) for referencing the output circuits thereon to either a standard reference voltage or an external reference voltage. The memory array (10) has a fused switch (22) associated therewith for referencing the charging voltage for the memory cells to either the positive reference voltage in the circuit or to an external variable voltage. The fused switches (18) and (22) are operable to switch to internal references for the normal operating mode and to the external variable voltages for the test mode.
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