4612640 Error checking and correction circuitry for use with an electrically-programmable and electrically-erasable memory array

Abstract

An on-chip checking and correction circuit extends the program/erase endurance of a semi-conductor memory array and catches data retention failures in individual memory cells of the array. For each data byte in the memory array, four parity bits are computed using a modified Hamming Code and stored in additional bit cells associated with that data byte. During read and write operations, check bits are calculated using the same Hamming Code and used to correct single-bit errors; error checking and correction is repeated if necessary up to a predetermined number of tries.