一個快速鎖定460.1MHz至6.177GHz之全數位式鎖相迴路的設計

Abstract

This thesis presents a design of fast-locking and wide-range all-digital phase locked loop (ADPLL). The locking procedure is partitioned into two modes including the Frequency Acquisition mode and the Phase Tracking mode. In the Frequency Acquisition mode, a novel frequency locking method called Regula Falsi is used for faster frequency locking. No matter the transfer curve of the digitally controlled oscillator (DCO) is linear or not, the method guarantees the frequency can always be locked. In addition, the frequency can be locked within two steps if the DCO has a linear transfer function. In the Phase Tracking mode, the ADPLL adopts two different loop bandwidths. The design first issues a wider loop bandwidth to speed up the phase tracking. After the phase is locked, the loop bandwidth is adjusted to a smaller one to reduce the phase noise and jitter. The circuit has been implemented in TSMC 90nm CMOS technology. The core area is 0.0646 mm2 and the whole chip area with bonding pads is 0.709 mm2. Measurement results show that the lock-in time of frequency takes 5 cycles and the lock-in time of phase is 3 cycles. The output frequency range is from 460.1 MHz to 6.177 GHz. The pk-pk jitter at 480 MHz output is 1.9% U.I., at 3 GHz output is 11.7% U.I., at 5 GHz output is 7.0% U.I., and at 6 GHz output is 5.1% U.I. Under the 6 GHz output frequency, the phase noise at 1 MHz offset is -81.68 dBc/Hz and at 10 MHz offset is -108.22 dBc/Hz. The ADPLL achieves a power efficiency of 9.2370 mW/GHz.