40 nm 1T–1MTJ 128 Mb STT-MRAM With Novel Averaged Reference Voltage Generator Based on Detailed Analysis of Scaled-Down Memory Cell Array Design

Abstract

The development of STT-MRAM technology is currently in progress and has been successively disclosed by major LSI vendors recently. In order to advance STT-MRAM technology and expand its areas of application, challenges relative to further device scaling need to be addressed. In this study, an increased wiring resistance in a deep sub-100 nm process by which the read operation yield is degraded was analyzed. The yield degradation was quantified by analyzing the conventional cell array using Monte-Carlo SPICE simulations. A new circuit was proposed to decrease the fail bit rate by an averaged reference voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ref</sub> ) generator. The simulated results indicated that the new Vref generator improved the fail bit rate by 1 order of magnitude compared to the conventional array. To demonstrate the circuit operation, a 128 Mb STT-MRAM chip was designed and fabricated using 40 nm CMOS and 37 nm MTJ technologies. For the first time, the chip measurements successfully demonstrated the operation of the proposed device-variation tolerant array architecture with the averaged V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ref</sub> generator, presenting a 30 ns read access time.