3-Level Buck Converter Design Space Exploration Results

Abstract

Having presented the theoretic operation of the 3-level Buck converter, and the expected benefits that would result from its application as a low-power fully integrated step-down converter, the corresponding design space exploration is presented in this chapter. First, the same output ripple constraint as in case of the classical Buck converter is applied; and the results show an expansion of the possible designs space, due to its relatively lower output ripple. In this sense, an optimized design with higher power efficiency and more reduced area is obtained. However, a new design space constraint is presented from the requirement to provide a wide output current range. This new context demands some kind of switching frequency modulation to keep an acceptable power efficiency when very low output current is provided. Consequently, a proportional modulation (Arbetter and Maksimovic, itPower Electronics Specialists Conference, 1997, PESC’97 Record, 28th Annual IEEE, St. Louis, MO, June 1997) of the switching frequency as a function of the output current (provided that the converter is DCM operated), is proposed. The main drawback of this proposal is an output ripple increase as both Io and fs become lower. Therefore, the new constraint requires to keep the output ripple below 50 mV in the output current range of 5 mA → 100 mA. Obviously, this results in a stronger reduction of the design space, and another optimized design is found providing poorer efficiency and bigger area occupancy (which is still better than the classical Buck counterpart). Finally, a suboptimum design selected, to be implemented in the chip to be tested, is presented because of practical considerations about the feasibility of the required control circuitry.