3D Wire Bondless Integration: The Future of Silicon Carbide (SiC) Packaging

Abstract

Wide bandgap (WBG) semiconductors are revolutionizing the world of power electronics. They have the potential to bring about an unprecedented increase in power density. The ability to switch at ultrafast rates, coupled with the promise of high temperature operation, make these devices extremely desirable. However, having superior semiconductor devices will not automatically translate to superior package characteristics. In real applications, the performance of a power device is only as good as the package allows. One of the major drawbacks plaguing contemporary power modules is the wire-bonded interconnection. Wire bonds offer a high parasitic inductance. This paper presents a novel wire bondless SiC power MOSFET packaging technique. A commercially available bare die was reconfigured into a chip-scale package. The new form factor enabled the MOSFET to be bonded to a patterned FR4 substrate using flip-chip bonding. The electrical interconnection between the package and the substrate was established using solder balls — thus eliminating the requirement for wire bonds. The motivation for using a wire bondless method was a reduction in stray parasitic inductances and an increase in the thermo-mechanical reliability. Lower parasitic inductances will facilitate high switching frequencies which will promote miniaturization, a reduction in electromagnetic interference (EMI), and lead to lower switching losses. The proposed approach was demonstrated to reduce the parasitic loop inductance by a fctor of > 3× as compared with wire bonded modules.