3D process simulation-assisted device failure analysis with virtual defect injection in IC layout

Abstract

The development and use of nanotechnology has enabled the creation of submicron electronic devices with unprecedented levels of functionality, speed, and efficiency. While most of the semiconductor industry and its consumers are becoming increasingly dependent on nanoelectronics, these devices are becoming more susceptible to defects and transient faults. Non-Visual Defects (NVD) is a category of semiconductor material and process induced defect that cause electrical failures but are not detected with visual wafer inspection tools (Findlay et al., 2016 [1] and Kim et al., 2009 [10]) or with fault localization tools. Devices with NVD may fail at any stage of their life cycle and may benefit from complex Failure Analysis (FA) investigations including software support to analyze design and diagnostic data. For a higher FA success rate, these investigations can be further supplemented with Technology Computer-Aided Design (TCAD) Process Simulation software to simulate a failure prior to actual physical analysis on limited device samples. In this work, we will showcase an innovative technique for simulating NVD using a 3D process model to pinpoint the exact process step where the defect was introduced. By injecting a new virtual defect layer (which can be autonomously introduced by an FA engineer) in the original device data, we can emulate the failing device. We also present a real-life case study where defect simulation correlates well with the actual Transmission Electron Microscope (TEM) cross-section results.