3D network-on-chip design for embedded ubiquitous computing systems

Abstract

A novel 3D NoC topology for embedded ubiquitous computing is proposed.A minimal routing algorithm with path diversity in the 3D NoC Topology is used.A power efficient architecture design for NoC-based embedded ubiquitous computing is introduced. Ubiquitous High-Performance Computing applications, such as cyber-physical systems, sensor networks and virtual reality require the support of terascale embedded systems that can deliver higher performance than current systems. Multi-cores, many-cores and heterogeneous processors are becoming the typical design choices to satisfy these requirements. Inter core communication has been one of the major challenges as it affects the bandwidth and power consumption of the multi-cores processors. Network-on-Chips (NoCs) present a fast and scalable interconnection solution to fulfill the requirements of Ubiquitous High-Performance Computing applications. This paper proposes a novel 3D Network-on-Chip called Octagon for Ubiquitous Computing (OUC) that is designed for Embedded Ubiquitous Computing Systems. OUC provides low network diameter and path diversity. Simulation results show that the proposed topology achieves a significant decrease in latency and an average 21.54% and 12.89% improvement in average throughput under hotspot and uniform traffic pattern respectively.