3D Modeling of Complex Combinations of Dies, Packages, Lead Frames, Sockets and Test Boards for Electrical, Thermal and Manufacturing Verification of Advanced Semiconductor Devices

Abstract

The software process described permits putting unlimited layers of dies and substrates in the same CAD database where many advanced optimizations and tunings can be accomplished on the entire electronic system simultaneously. Gates and swappable memory and FPGA pins may be optimally selected to reduce wire length and the number of routing layers. Die placement may also be optimized across multiple subtrates for the same purpose. Interposers between substrates or side routing can be implemented and I/O locations optimized for maximum performance. Native scripts may be used to generate composite electrical models in the major electrical analysis tools that define 3D geometries precisely without 2-1/2 D abbreviations. Exact ACIS and Step models define the complex stackups for Thermal analysis in major Thermal Modeling softwares. All these models are created with high speed which enables the multiple design cycle iterations necessary for the refinement of a quality product. All relevant material properties and ports are exported with the 3D graphical data. Where appropriate changes are initialised back into parametric models. Customizations of the process by the users are routine.