Abstract
Targeting on low power consumption and high spatial resolution, the CPV-4 SOI pixel sensor has been developed. Its pixel circuit requires about 120 transistors to implement the analog-digital mixed signal processing functionality within a compact pixel area of 17 μm × 21 μm. By utilizing 3D vertical integration, sensing diode and analog front-end are realized in the lower-tier chip, while hit information storage and sparse readout are achieved in the upper-tier chip, thereby minimizing its pixel size and power consumption. This work presents the pixel circuit design and the test results on the completed 3D chips. The feature of SOI pixel process and the 3D integration are also highlighted in this article.
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