3D ICs-power Analysis Using Cylindrical and Co-axial Through Silicon Via (TSV)

V Vinoth Thyagarajan,S Rajaram

doi:10.19026/rjaset.9.1388

Abstract

In this study, analytical model and electrical equivalent circuit of Through Silicon Via (TSV) is analyzed. Through silicon Vias form an integral component of the 3-D IC technology by enabling vertical interconnections in 3-D ICs. Among various types, the performances of the simplified lumped TSV model of cylindrical and co-axial type were studied. The performance analyses of these structures were presented by introducing these structures between the tiers of digital circuits. The power consumption of the transistor level digital circuits for single tier without TSV and multiple tiers with cylindrical TSV and Co-axial TSV was simulated using Virtuoso Schematic Editor of Cadence. The comparison for cylindrical and co-axial TSV model with different level tiers were tabulated and performed.

Highlights

To increase the functionality and Integration density, the recent advancements in semiconductor processing technologies have enabled three dimensional circuit designs and implementation of heterogeneous systems in the same platform, i.e., Flash, DRAM and SRAM placed on top of logic devices and microprocessor cores (Knickerbocker et al, 2008). 3-D Integration has been considered as the leading technology to overcome the planar IC scaling down limitations such as increased power consumption, wire delay, process variation and cost with the technical node evolution. 3D IC technology helps in mitigating the interconnect problems by reducing the global interconnect wiring length and simultaneously reducing the chip area
Today there is a variety of Through Silicon Via (TSV) structures fabricated and characterized, with various sizes, heights, aspect ratios, materials, densities and processes such as cylindrical TSV, tapered TSV, annular TSV, co-axial TSV, etc
The objective of this study is to analyze the parameters of TSV Model and the performance comparison of Cylindrical and Coaxial TSV RLC Model by introducing these structures between the tiers are verified by using the Virtuoso Schematic Editor

Summary

Introduction

To increase the functionality and Integration density, the recent advancements in semiconductor processing technologies have enabled three dimensional circuit designs and implementation of heterogeneous systems in the same platform, i.e., Flash, DRAM and SRAM placed on top of logic devices and microprocessor cores (Knickerbocker et al, 2008). 3-D Integration has been considered as the leading technology to overcome the planar IC scaling down limitations such as increased power consumption, wire delay, process variation and cost with the technical node evolution. 3D IC technology helps in mitigating the interconnect problems by reducing the global interconnect wiring length and simultaneously reducing the chip area. Many long interconnects required in 2D chips can be replaced by a 3-D chip by short vertical interconnects. This improves the circuit performance and reduces the total wiring length needs for a system (Van Olmen et al, 2008). Through Silicon Via (TSV) is a vertical interconnect element which connects multiple dies and routes the electrical signal and power supply path through all the chips in the stack. TSVs shorten the chip-to-chip interconnects, enable products with higher electrical performance, lower power consumption, wider bandwidth, higher density, smaller form factor, lighter weight and eventually lower cost (Xu and Lu, 2012). Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics

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