3D-HEVC Bipartition Modes Encoder and Decoder Design Targeting High-Resolution Videos

Abstract

This paper presents hardware designs for the encoder and decoder of the 3D-High Efficiency Video Coding (3D-HEVC) bipartition modes targeting real-time processing of high-resolution videos. These hardware designs include the depth modeling modes 1 (DMM-1) and 4 (DMM-4). The encoder was designed using a simplification in the DMM-1 algorithm with the advantage of better using the hardware resources and without coding efficiency loss. The encoder architecture was designed in a scalable structure supporting different block sizes and reaching different throughputs according to the application requirements. The decoder was designed sharing resources between DMM-1 and DMM-4 execution and supporting all available block sizes. Both architectures were synthesized for 65- and 28-nm technologies, being capable of achieving real-time processing for ${1920}\times {1080}$ videos at 30 frames/s.