Abstract
Throughout this paper, signal integrity (SI) problems in high -speed PCB design have been addressed as being a result of via stubs and fabrication tolerances that are present throughout PCB transmission lines. Robust PCB design must be ensured as signal rise and fall times have shortened, which is modeled within the 3D EM simulation environment of CST Studio. It is shown that the insertion loss of the signal is affected by the resonance frequency of the via stub, and impedance mismatches throughout the transmission lines. Shielding techniques have been investigated to combat these effects on SI, and have shown a significant improvement in bandwidth as a result.
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