Abstract

This work reports on the properties of cubic silicon carbide (3C-SiC) grown epitaxially on a patterned silicon substrate composed of squared inverted silicon pyramids (ISP). This compliant substrate prevents stacking faults, usually found at the SiC/Si interface, from reaching the surface. We investigated the effect of the size of the inverted pyramid on the epilayer quality. We noted that anti-phase boundaries (APBs) develop between adjacent faces of the pyramid and that the SiC/Si interfaces have the same polarity on both pyramid faces. The structure of the heterointerface was investigated. Moreover, due to the emergence of APB at the vertex of the pyramid, voids buried on the epilayer form. We demonstrated that careful control of the growth parameters allows modification of the height of the void and the density of APBs, improving SiC epitaxy quality.

Highlights

  • In the last few years, significant interest in silicon carbide (SiC) has emerged due to the possibility of high power and high current device fabrication

  • We investigate a particular compliant substrate able to reduce the number of SFs in the epilayer surface

  • We investigated the morphology of the surface and recognized the presence of extended defects, such as anti-phase boundaries (APB), related to the patterning structure

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Summary

Introduction

In the last few years, significant interest in silicon carbide (SiC) has emerged due to the possibility of high power and high current device fabrication. Transition from gasoline to hybrid and to fully electric vehicles is occurring. This transition is part of a green revolution, which is going to be the trigger for the development of new devices for electric motors and for high voltage energy saving applications driving the society to a more sustainable economy. Despite the enormous interest and despite the enormous high power device market growth, the material is scarcely mature for the standards required in the microelectronic industry and is extremely expensive. The main limitation for device manufacture comes from the wafer fabrication that allows the presence of a high density of defects in the epilayer

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