38dB Tuning Range Coupled VCO Based Divider Architecture with 68uW Power @2.0 GHz in 65nm CMOS

Abstract

Listen

Translate article

Super harmonic division at low power consumption in unilaterally injection locked current controlled ring oscillator system has been explored. Frequency divider for PLL output stage divides a 2.0GHz PLL clock by 2 while consuming just 68uW from a 1.2V power supply. Current Controlled Ring oscillator has been made using single ended inverter stage in 65nm cmos. Two new architectures are proposed to design such Injection Locked Frequency Dividers (ILFD). Compared to the conventionally used True Single Phase Clocking (TSPC) dividers for power improvement, this method gives reduction of 93 % to 67 % in total power consumption for division across the Process corners and across the tuning range of 78:8 %. The divider achieves a phase noise performance of -91dBc/Hz@1mHz offset and just takes an area of 43 m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Another advantage of this circuit is that, it can be used inside as well as outside the PLL itself improving the performance as the injection locked stage filters out the jitter introduced by the buffer stages.