32nm strained nitride MTP cell by fully CMOS logic compatible process

Abstract

A 32nm MTP cell with a nitride-based storage node using 32nm strained Si process are demonstrated with an ultra small cell size of 0.0528µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> by a 32nm strained-CMOS fully logic compatible process. A self-aligned tiny nitride storage node is placed in the narrow spacing of two 32nm transistors by a merged transistor spacer mingled with a strained nitride of 32nm strained Si process. The twin-gate cell uses the source side injection (SSI) to obtain 100 times of on/off window by a low program voltage of 3.5V within 1msec. A good reliability in retention and disturb is exhibited due to the inherently decoupling of storage node and transistor gate oxide in this cell, even when gate oxide is thinner than 16Å with 32nm gate length only.