32nm FinFET Based PLL

Abstract

The demand for low power based circuits increases as the size of channel length decreases. But as channel length decreases it is difficult to use CMOS based circuits due to problems in its fundamental material, short channel effect and high leakage. Thus FinFET technology can be used as an alternative to classical MOSFET, to achieve low power application. The effectiveness of various Double Gate in Mixed Signal(MS) circuit level design is less explored. Phase Locked Loop (PLL) is one of the important MS circuit and are integral part of many electronic system. Extracting advantages of FinFET over above mentioned issues in PLL, this paper proposes two design of PLL using novel device DGMOS FinFET at 32nm technology. The first design of FinFET based PLL uses FinFET in shorted gate (SG) mode & the second design uses FinFET in independent gate (IG) mode for the design of Phase Frequency Detector (PFD) block. The designed circuits are simulated using HSPICE by Synopsis with 32nm FinFET technology with power supply voltage of 0.8V. Performance of designed PLL are analyzed at operating frequency of 500MHz. The comparative analysis of all the designs of PLL shows that Modified FinFET based PLL at 32nm shows better performance in terms of faster locking period at 38.34ns, high frequency operation from 500MHz to 11GHz with smaller area requiring lesser no. of transistors & having power dissipation of 86.36 µW which is comparatively low.