30 nm Tungsten gates etched by a low damage ICP etching for the fabrication of compound semiconductor transistors

Abstract

This paper investigates high resolution, low damage dry etching of tungsten, a suitable candidate for gate metallization in compound semiconductor based high mobility channel device, by using a Surface Technology Systems Ltd. (STS) inductively coupled plasma (ICP) etching system with SF 6 and C 4F 8 process gases. Low stress tungsten films with thicknesses in the range 100–200 nm were deposited on GaAs substrates for the etching tests using a Plassys MP900S sputter coater. To evaluate the plasma-induced damage in the ICP etching process, GaAs based high electron mobility transistor (HEMT) type layer structures with channels buried less than 20 nm from the surface, were grown by molecular beam epitaxy (MBE). Subsequently, Van der Pauw (VdP) structures were fabricated to enable determination of the impact of the etching on room temperature sheet resistivity, carrier concentration and electron mobility. The investigation of the effect of various etching parameters on the profile, minimum feature size and electrical damage has led to a low damage ICP etching process with minimum feature size of 25 nm, which is suitable for the fabrication of compound semiconductor based high mobility channel devices.