30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays

Abstract

Planar CMOS transistors have been fabricated to evaluate the 70 nm technology node using conventional transistor design methodologies. Conventional CMOS transistors with 30 nm physical gate length were fabricated using aggressively scaled junctions, polysilicon gate electrode, gate oxide and Ni silicide. These devices have inversion Cox exceeding 1.9 /spl mu/F/cm2, n-MOS gate delay (CV/I) of 0.94 ps and p-MOS gate delay of 1.7 ps at V/sub cc/=0.85 V. These are the smallest CV/I values ever reported for Si CMOS devices. The transistors also show good short channel control and subthreshold swings. The n-MOS and p-MOS have drive currents equal to 514 /spl mu/A//spl mu/m and 285 /spl mu/A//spl mu/m respectively with I/sub off/ at or below 100 nA//spl mu/m at Vcc=0.85 V. The saturation gm is equal to 1200 mS/mm for n-MOS and 640 mS/mm for p-MOS. These are among the highest gm values ever reported. The junction edge leakage is reasonably low with less than 1 nA//spl mu/m at 1.0 V and 100 C for both n-MOS and p-MOS. These encouraging results suggest that the 70 nm technology node is achievable using conventional planar transistor design and process flow.