3-D Heterogeneous Integration of RRAM-Based Compute-In-Memory: Impact of Integration Parameters on Inference Accuracy

Abstract

Three-dimensional heterogeneous integration (3-D-HI) has been proposed as a potential method to stack a large amount of embedded memory required in state-of-the-art compute-in-memory (CIM) artificial intelligence (AI) accelerators. While embedded nonvolatile memory, such as resistive RAM (RRAM), is a promising alternative to static random access memory (SRAM)/dynamic random access memory (DRAM) as a CIM synaptic device owing to high density, low leakage, and nondestructive read, thermal-induced device conductance drift remains a challenge. High-temperature-driven lower retention can be more significant in dense memory-logic 3-D integration due to increased volumetric power, which has not been studied in prior work. The scope of this work is to quantify the thermal impact of different 3-D-HI architectures on the reliability of 3-D-integrated binary RRAM devices for CIM applications. A device-integration-application reliability evaluation methodology is proposed, using which 3-D integration architectures and logic-memory partitioning configurations are benchmarked. Due to higher junction temperatures for memory tier in both five-tier monolithic 3-D (M3D) and five-tier through silicon via (TSV)-based 3-D compared to the 2-D baseline, the drop in inference accuracy at ten years is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\approx 80$ </tex-math></inline-formula> %. For our assumed device, integration, and application parameters, a three-tier configuration provides a balanced design option between thermal and application performance. The integrated benchmark framework is released on GitHub ( <uri xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">https://github.com/i3dsystems/3D_CIM_thermal_v1.0</uri> ) as an open-source tool for the research community.