2x2 and 4x4 CMOS Switching Matrices for 0.01-12 GHz Applications

Abstract

This paper presents 2times2 and 4times4 switching matrices implemented in 0.13 um CMOS. The switches are based on a series-shunt design with inductive matching at the input and output ports. High substrate resistance together with deep trenches is used for low insertion loss. A 2times2 switch matrix (also called a transfer switch) results in an insertion loss and isolation of 1.3-2.3 and 48-40 dB, respectively, at 2-12 GHz. The 2times2 switch is used to build a single-chip 4times4 CMOS switch matrix with an insertion loss and isolation of 2.3-4.5 and 57-35 dB, respectively, at 2-12 GHz. The measured input PldB and IP3 is 11-12 dBm and 29-30 dBm, respectively, both at 6 GHz and at 12 GHz. The chip area is 0.84times0.79 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (2times2) and 0.95times1.52 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (4times4), and the switch matrices does not consume any current from a 1.5 V supply.