2-Phase Energy-Efficient Secure Positive Feedback Adiabatic Logic for CPA-Resistant IoT Devices

Abstract

Internet of Things (IoT) devices are mostly areas constrained and operate on a limited battery supply and therefore have tight energy budgets. Lightweight cryptography (LWC) such as PRESENT-80 allows for minimal area usage and low energy for secure operations. However, CMOS implemented LWCs are vulnerable to side-channel attacks such as Correlation Power Analysis (CPA). Adiabatic Logic is an emerging circuit design technique that can reduce energy consumption and be CPA resistant. Many existing adiabatic logic families use a 4-phase clocking scheme which pays a large area penalty. Thus, in this paper, we propose 2-EE-SPFAL, a 2-phase clocking scheme implementation of an existing adiabatic family known as EE-SPFAL. We explore 2-phase sinusoidal waves in terms of energy efficiency and security. To demonstrate energy savings and security against CPA attacks we construct one round of PRESENT-80 in both CMOS and 2-EE-SPFAL. Simulations were conducted using 45nm technology in Cadence Spectre. At 12.5MHz, our results show an average energy saving of 50% between CMOS and 2-EE-SPFAL. Furthermore, we performed a CPA attack on both the CMOS and 2-EE-SPFAL implementation and determined that the CMOS key could be retrieved while the adiabatic key was kept hidden.