Abstract
In this paper, the key reliability characteristics of the 3D NAND technology are discussed and compared to the 2D NAND corresponding features. It is shown that 3D NAND can achieve up to 50% improvement of the intrinsic cell threshold voltage (V T ) distribution width, due to increased cell size and between — cell distance. Two 3D NAND specific reliability aspects are discussed in detail. The presence of the polysilicon channel in 3D NAND array causes temperature related cell current and threshold voltage variations. Also, the CMOS Under the Array (CuA) architecture requires the introduction of the GIDL — Assisted Erase technique, which must be properly designed and optimized not to impact the array reliability performance.
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