2D materials as semiconducting gate for field-effect transistors with inherent over-voltage protection and boosted ON-current

Qingkai Qian,Zhaofu Zhang,Gaofei Tang,Zheyang Zheng,Jin Wei,Kailun Zhong,Jiacheng Lei,Kevin J Chen

doi:10.1038/s41699-019-0106-6

Abstract

Various 2D/3D heterostructures can be created by harnessing the advantages of both the layered two-dimensional semiconductors and bulk materials. A semiconducting gate field-effect transistor (SG-FET) structure based on 2D/3D heterostructures is proposed here. The SG-FET is demonstrated on an AlGaN/GaN high-electron mobility transistor (HEMT) by adopting single-layer MoS2 as the gate electrode. The MoS2 semiconducting gate can effectively turn on and turn off the HEMT without sacrificing the subthreshold swing and breakdown voltage. Most importantly, the proposed semiconducting gate can deliver inherent over-voltage protection for field-effect transistors (FETs). Furthermore, the self-adjustable semiconducting gate potential with drain bias can even boost the ON-current while guaranteeing the safe operation of FET. In implementing the semiconducting gate, the layered two-dimensional materials such as the adopted MoS2 have several important benefits such as the feasibility of high-quality crystals on different gate dielectrics and the good controllability of semiconducting gate depletion threshold voltage by the layer thickness. The demonstrated semiconducting gate as over-voltage protection for HEMT can be extended to other FETs, which can become another advantageous arena for the possible applications of the layered two-dimensional materials.

Highlights

IntroductionField-effect transistor (FET), as a voltage-driven device with large input impedance, is at the heart of modern semiconductor technologies (e.g., CMOS, TFT, compound semiconductor high-electron mobility transistor (HEMT), etc.) supporting a wide range of existing and emerging applications.[1,2,3,4,5,6,7] These applications include low-power field-effect transistors (FETs) in logic and analog IC’s for high-speed computing and IoT,[4,5] HEMTs/ MISFETs based on compound semiconductors (e.g., GaN, SiC) for high-power and high-frequency switchings.[6,7] Despite the above advantages and broad applications, the voltage-driven FETs have a drawback of being very susceptible to the overloaded gate voltage
The metal gate (MG) is formed with 5 nm/6 nm Ni/Au
Dangling-bond-free 2D materials such as MoS2 are especially suitable for the implementation of semiconducting gate field-effect transistor (SG-field-effect transistors (FETs)), as high-quality thin equipotential for a non-zero drain bias during the gate voltage films could be transferred or deposited on various gate dielectrics clamping

Summary

Introduction

Field-effect transistor (FET), as a voltage-driven device with large input impedance, is at the heart of modern semiconductor technologies (e.g., CMOS, TFT, compound semiconductor HEMT, etc.) supporting a wide range of existing and emerging applications.[1,2,3,4,5,6,7] These applications include low-power FETs in logic and analog IC’s for high-speed computing and IoT,[4,5] HEMTs/ MISFETs based on compound semiconductors (e.g., GaN, SiC) for high-power and high-frequency switchings.[6,7] Despite the above advantages and broad applications, the voltage-driven FETs have a drawback of being very susceptible to the overloaded gate voltage. A large over-voltage gate stress can result in severe threshold voltage instabilities[8,9,10,11] or even lead to long-term degradation (e.g., breakdown) of the gate dielectric or semiconductor barrier layer between the gate and the channel.[12,13,14] power FETs are designed to sustain large drain bias, they are vulnerable to the forward gate overstress. Various gate over-voltage protection techniques have long been developed for FETs.[15,16,17] These protection schemes can be categorized into two types: current limiting and voltage limiting.[15] all these solutions require external peripheral circuits or components such as the bootstrapped FETs, Zener diode, etc, which could lead to higher cost and increased parasitics, and impose extra difficulties for monolithic integration

Methods

Results

Conclusion