28 nm UTBB-FDSOI energy efficient and variation tolerant custom digital-cell library with application to a subthreshold MAC block

Abstract

This paper presents the design of digital logic cells for subthreshold applications using 28 nm ultra-thin body and box fully depleted silicon on insulator technology. The sizing approach relies on balancing pull-up/pull-down networks (PUN/PDN) strength ratio by applying an additional forward back-gate biasing (FBB) voltage to the back-gate of PMOS transistors. The minimum width of PMOS and NMOS transistors have been chosen by taking the narrow width effect into account. Moreover, to increase the functional yield of the logic cells, a trade-off has been made between I on /I off ratio and energy consumption through increasing the channel length by 4 nm. Energy consumption of logic gates analyzed using ring-oscillators consisting of basic logic gates. It has been shown that balancing logic gates through applying an additional FBB to the PMOS back-gate instead of up-sizing PUN results in 30% lower energy consumption in ring-oscillators. An 8-bit multiply-accumulate (MAC) block was synthesized using the fully customized logic cells with asymmetric back-gate biasing. Compared to a state-of-the art MAC, the energy consumption of our MAC was improved by 21% at a relatively high speed (147 MHz).