28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique

Abstract

We propose a new 2T mask read only memory (ROM) with dynamic column source bias control technique, which enables achieving both high-speed operation and low power consumption. It is also possible to overcome the inherent problem of crosstalk between the bitlines. The fabricated 128-kb ROM macro using 28-nm high- k and metal-gate CMOS bulk technology realizes 0.72 ns read access time at the typical 0.85-V supply voltage, which is comparable to that of recent high-speed embedded static random access memories. The measured dynamic power dissipation is reduced by 50% compared to the conventional 2T ROM. The standby leakage can also be reduced to half that of conventional macros.