28-GHz Passive Frequency Tripler With n-Type Varactors in 45-nm SOI CMOS

Abstract

A 28-GHz passive frequency tripler for 5G New Radio (NR) is demonstrated in 45-nm SOI CMOS. A symmetric antiparallel pair of series varactor (SAPSV) topology is proposed to reduce the conversion loss (CL) and increase the output power by realizing symmetric $C$ – $V$ curves with only n-type varactors and simplified dc biasing. Compact on-chip LC networks provide 13.6− and 20.1-dBc rejection for fundamental and second harmonics, respectively, from 27.1 to 32.4 GHz (17.8%). The measured minimum CL is 24.3 dB, and the maximum output power is −8 dBm. Conversion loss variation is not more than 3 dB when the input power range varies from 8 to 20 dBm. The tripler only adds a 9.66-dB integrated phase noise measured from 1 to 100 kHz at 28.95 GHz.