26.1 A Source-Driver IC Including Power-Switching Fast-Slew-Rate Buffer and 8Gb/s Effective 3-Tap DFE Receiver Achieving 4.9mV DVRMS and 17V/µs Slew Rate for 8K Displays and Beyond

Kyungho Ryu,Hyun-Wook Lim,Jung-Pil Lim,Kyongho Kim,Ji-Yong Jeong,Kil-Hoon Lee,Jae-Youl Lee,Siwoo Kim,Seongjong Yoo,Yongil Kwon

doi:10.1109/isscc42615.2023.10067592

Abstract

With the growing demand for higher resolution and faster refresh rate displays, the nextgeneration TVs and gaming monitors are expected to accommodate 8K resolution with a refresh rate of 120Hz and beyond. In such display systems, about one thousand channels will be integrated on a source driver IC (SD-IC), one-horizontal line (1-H) time will be reduced to under 1.8µs, and the total data throughput of the interface between timing controller (TCON) and SD-ICs will surpass 190Gb/s. This will result in deterioration of display quality due to the channel offset, insufficient channel settling time, and bandwidth limitation of intra-panel interface [1–5]. As shown in Fig. 26.1.1, three key solutions for: (1) large deviation of root-mean-square voltage output (DVRMS), (2) settling limitation due to panel load resistance and capacitance, and (3) interface channel insertion loss of over 30dB with the process of the high-voltage SD-IC that is limited to 0.18µm CMOS, are required for next-generation 8K SD-IC. To overcome these challenges, this paper presents an 8K SD-IC in 0.18µm CMOS, also shown in Fig. 26.1.1. Most SD-IC research to date has tried to reduce offset by increasing the size of mismatched transistors or adopting offset cancellation in the buffer, which requires timeconsuming switching operations using multiphase clocks, and thus it is impossible to meet <1.8µs 1-H time [1]. In addition, the data rate of the receiver is limited due to stringent decision feedback equalizer (DFE) timing constraints in 0.18µm processes [5]. In this paper, a simple power switching structure is suggested to solve the non-uniform image quality between channels. In addition, a fast-slew-rate (FSR) circuit is proposed to minimize settling time for <1.8µs 1-H time. Finally, an 8Gb/s display interface receiver, including an effective 3-tap adaptive equalizer (EQ), is proposed.

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