260 Mb/s mixed-signal single-chip integrated system electronics for magnetic hard disk drives

Abstract

A single-chip mixed-signal 3CI integrates a PRML read channel (RDC), an ATA hard disk controller (HDC), a microcontroller (/spl mu/C) (containing an ARM7TDMI 32b RISC microprocessor (/spl mu/P), ROM and RAM), and a motion control servo block, realized with 1.45 M transistors. Partial response maximum likelihood (PRML) read channels are realized in BiCMOS and CMOS. Critical RDC blocks-such as an extended partial response, class 4 detector (EPR4), servo, finite impulse response (FIR) and interpolated timing recovery (ITR) in digital CMOS circuitry enhance volume manufacturability. CMOS read channels can be leveraged in system-level integration and, typically, benefit first from rapid process/lithography improvements.