Abstract

This paper presents two single-pole, double-throw (SPDT) mm-wave switches for Ka-band phased-array transceivers, fabricated with a 65-nm complementary metal oxide semiconductor (CMOS) process. One switch employs cross-biasing (CB) control with a single supply, while the other uses dual-supply biasing (DSB) control with positive and negative voltages. Negative voltages were generated internally, using a ring oscillator and a charge pump. Identical gate and body floated N-type metal oxide semiconductor field effect transistors (N-MOSFETs) in a triple well were used as the switch core transistors. Inductors were used to improve the isolation between the transmitter (TX) and receiver (RX), as well as insertion loss, by canceling the parasitic capacitance of the switch core transistors at resonance. The size of the proposed radio frequency (RF) switch is 260 μm × 230 μm, excluding all pads. The minimum insertion losses of the CB and DSB switches were 2.1 dB at 28 GHz and 1.93 dB at 24 GHz, respectively. Between 25 GHz and 34 GHz, the insertion losses were less than 2.3 dB and 2.5 dB, the return losses were less than 16.7 dB and 17.3 dB, and the isolation was over 18.4 dB and 15.3 dB, respectively. The third order input intercept points (IIP3) of the CB and DSB switches were 38.4 dBm and 39 dBm at 28 GHz, respectively.

Highlights

  • The recent explosive growth of mobile traffic has created a demand for increased bandwidths and faster data rates in telecommunication

  • For terrestrial-satellite backhaul network communication, 17.7–20.2 GHz for downlink and 27.5–30 GHz for uplink are considered in the Ka-band [1,2,3]

  • Due to the short wavelengths corresponding to these frequency bands, compact phased-array antennas can be realized using wafer-scale, on-chip antennas or printed circuit-board antennas, as well as mm-wave, complementary metal oxide semiconductor (CMOS)-integrated circuit technology [4,5,6,7]

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Summary

Introduction

The recent explosive growth of mobile traffic has created a demand for increased bandwidths and faster data rates in telecommunication. These supply voltages control only source of the transistor. The other switch core uses dual supply biasing (DSB) control with positive the gate voltage, VC , while the drain and source are grounded, i.e., VS,D = 0 V. The negative supply voltage is generated byby anan internal negative voltage generator (NVG)

Block diagram of the proposed
Cross-sectional
Implementation and Measured Results
13. Insertion losses
Conclusions

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