24 秭赫互補式金氧半低雜訊放大器、壓控振盪器及開關之研製

Abstract

In this thesis, a 24 GHz LNA, VCO, and SPST switch have been designed and fabricated in a standard TSMC 0.18 μm 1P6M CMOS technology. A design method of CMOS LNA is used to render the optimum source resistance (Ropt) close to 50 Ohm and Zin* = Zopt by using small devices and small bias currents. This LNA chip achieves a peak gain of 13.5 dB and a noise figure of 4.7 dB at 24 GHz. The supply voltage and supply current are 1 V and 8.3 mA, respectively. The input and output return loss are lower than −10 dB. The input referred 1-dB compression (P1dB) is −7 dBm. The chip size is 0.64 mm × 0.48 mm. The oscillation amplitude is enhanced by transformer-feedback to lower the phase noise. The supply voltage can be reduced since no extra voltage headroom is required by the transformer, thus the power consumption can be reduced. The VCO chip exhibits phase noise of −104.38 dBc/Hz at 1 MHz offset and an output tuning range of 400 MHz using NMOS varactor. The VCO consumes a dc power of 6 mW with a supply voltage of 1 V. The chip area is 0.52 mm × 0.34 mm. The on-resistance can be decreased by increasing the width of transistor, but capacitive coupling to the substrate will become significant. An LC resonant technique is proposed to decrease the insertion loss in the on-state and increase the isolation in the off-state. The switch achieves insertion loss and isolation of 0.7 dB and 25 dB, respectively. The input P1dB of the switch is 16 dBm. The effective chip size is only 0.17 mm × 0.23 mm.