23552-channel IC for single photon counting pixel detectors with 75 µm pitch, ENC of 89 e<sup>−</sup> rms, 19 e<sup>−</sup> rms offset spread and 3% rms gain spread

Abstract

We report on the novel method of an in-pixel offset and gain correction for implementation in multichannel hybrid detector readout circuits. A prototype ASIC consisting of 23552 square shaped pixels of 75 μm pitch was designed and fabricated in CMOS 130 nm technology. Each pixel containing charge sensitive amplifier, shaper, discriminator, correction circuits and two 14-bit counters has an equivalent noise charge of 89 e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> rms and dissipates only 25 μW. Tests prove its exceptional uniformity with an offset spread of 19e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> rms and the gain spread of only 3%, rms what is good enough for color X-Ray imaging. The paper presents the architecture of the ASIC, a transistor level novel schematic of key blocks used for offset and gain trimming, the testing procedure and its results.