20nA sub-threshold biased CMOS reference current source

Abstract

A low voltage low power CMOS reference current source is designed by biasing MOSFETs in the sub-threshold region. This current source operates with the battery of 0.8V & produces stable reference current of 20nA. The circuit has been designed using 180nm CMOS technology of Semiconductor Laboratory of ISRO India & simulated using “Analog design Environment” of Cadence. This reference current source provides a current sensitivity of 0.65 percent per volt with power supply voltage, a variation in reference current is just 0.001 percent with a variation of the load from 1 ohm to 1 Mega Ohm, temperature sensitivity of reference current is 0.032 percent per deg C & consumes just 232nW. This reference current source is quite suitable for biomedical applications & implantable devices where low voltage and low power stable reference current source is the primary requirement.