20101 機械工学が支援できる最先端デバイス(1) : Cu/low-k配線構造のCMPプロセスにおける有限要素法応力解析(機械工学が支援する半導体製造技術,OS1 機械工学が支援する微細加工技術(半導体・MEMS・NEMS))

Abstract

Porous low-k materials are required in the construction of LSI devices. However, the extremely low Young's modulus values of these materials result in peeling and/or stress corrosion cracking (SCC) of Cu interconnects during chemical mechanical planarization (CMP). We performed finite element method (FEM) analysis of stress during each step in CMP processing varying Young's modulus of interlayer dielectric (ILD) films. The results supported that the horizontal tensile stress concentrated especially at the edges of the isolated fine wiring, and that higher tensile stresses appeared at the step of barrier CMP. Moreover, the maximum values of tensile stress increased with the decrease of Young's modulus of low-k films. Shear stresses also increased with the increase of the difference of Young's modulus between materials. Since the cause of these stresses are due to the downward CMP pressure on the hard material (e.g. Cu) and the soft material (e.g. low-k film), which indented the soft materials, CMP process with a lower downward pressure and a structure with dummy pattern is recommended.