200 Mb wafer memory

Abstract

The realization of a high-capacity whole-wafer memory is described, including wafer configuration, chip architecture, process technology, and performance. The wafer is essentially a single-ported serial memory device. An innovative concept which utilizes any defective chips free from power failures has made possible a high-yield wafer-scale memory. The wafer includes an array of chips which have a DRAM (dynamic RAM) core and additional control logic known as the configuration logic (Conlog). Each Conlog is connected to its four neighbors by signal lines, which form logic networks on the wafer. An external controller transmits commands to each Conlog element to set up links between chips and configure a single contiguous data path known as a spiral. The spiral is configured on completion of wafer processing by external control software which implements chip test and linking of chips as a single-shaped data-flow chain. The DRAM core and Conlog are designed using a standard 1-Mb DRAM fabricated by the 1.3- mu m CMOS process. The waveform of the internal clock and output of the DRAM are shown as well as the output waveform of the receive terminal of Conlog. >