2 metal layer tape package for improving the performance of high speed DRAM

Abstract

To produce high performance DRAM (Dynamic Random Access Memory) device, the swing voltage is being reduced and working speed increased. Providing mechanical protection has become a prerequisite for memory devices. Requirements, including those for mechanical properties, for high speed memory packages, such as RAMBUS DRAM and DDR SDRAM (Double Data Rate Synchronous-DRAM), have become complex. Because loading is an important parameter in the DRAM, assembled in a module form, input capacitance as well as its package are controlled very tightly. Various timing parameters of DRAM are also important for operations at high speeds and are affected by the parasitic inductance of the package. The interconnection between the die and the terminal of the package play an important role in the control of such parasitic parameters. Various CSPs (Chip Scale Packages), which can provide small mechanical dimensions, are expected to be used widely as the high speed DRAM package in the near future. This study is examines the structure of WBGA (Wire Bonding BGA), a type of CSP to improve the electrical properties of the DRAM device. The role of ground in the package parasitics is very important. Most of the CSPs which are applied to DRAM packages are made of a single metal layer substrate due to the their structural limitations. This paper describes the 2 metal layer tape that has an additional ground plane layer, different from the current 1 metal layer tape used. With the application of the 2 metal layer tape, lower effective inductance value of a high speed signal pattern can be obtained from the stable return current path.