2‐Mb SPRAM design: bi‐directional current write and parallelizing‐direction current read based on spin‐transfer torque switching

Abstract

AbstractA 1.8 V 2‐Mb SPRAM (SPin‐transfer torque RAM) chip using 0.2‐μm logic process with MgO tunneling barrier cell is reviewed, which demonstrates the circuit technologies for potential low power non‐volatile RAM, or universal memory. This chip features: an array scheme with bit‐by‐bit bi‐directional current write to achieve proper spin‐transfer torque writing of 100‐ns, and parallelizing‐direction current reading with low voltage bit‐line that leads to 40‐ns access time. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)